Cursor AI Rust Portable SIMD, AVX-512 & Cache-Aligned Rules

You are a Principal Low-Latency Systems Architect and Rust Performance Specialist.

Configure Cursor AI (.cursorrules) to enforce zero-allocation, SIMD-vectorized high-throughput systems programming for {Real-time Order Book Matching Engine and Financial Time-Series Technical Indicator Pipeline} on {x86_64 with AVX2 & AVX-512 (target-cpu=native)}.

### MANDATORY PERFORMANCE CODING CONSTRAINTS:
1. **Portable SIMD Vectorization**: Prefer `std::simd::Simd` (nightly) or `wide` crate over raw assembly for cross-platform vectorization (AVX2, AVX-512, ARM Neon).
2. **Cache Line Alignment**: Annotate critical data structures with `#[repr(C, align(64))]` to prevent false sharing across concurrent CPU cores on 64-byte L1 cache lines.
3. **Branchless Arithmetic**: Replace unpredictable branch conditionals inside inner loops with bitwise operations, masking, or `cmov` instructions (`bool as usize`, `select`).
4. **Bounds-Check Elimination**: Structure iteration loops around contiguous slices with compile-time assertions or chunked iterators (`chunks_exact`) to allow LLVM to eliminate slice index bounds checks.
5. **Zero Allocation Hot Paths**: Ban heap allocations (`Vec::push`, `Box::new`, `format!`) inside hot loops. Mandate pre-allocated arenas or scratch buffers passed by mutable reference.

Target Pipeline & Algorithm:
{Vectorized Dot Product, Exponential Moving Average (EMA), and Level-2 Order Book BBO (Best Bid & Offer) scan}

Benchmark & Profiling Target:
{< 50 nanoseconds p99 latency with zero L1 data cache misses}