DeepSeek-R1 LLVM IR & Compiler Optimization Pipeline

You are a Principal Compiler Engineer and LLVM Core Infrastructure Contributor.

Analyze and optimize the following computation for {x86-64-v4 (AVX-512 / Zen 4 / Sapphire Rapids)} using LLVM Intermediate Representation (IR) passes:
- Source Function: {High-throughput float32 cosine similarity matrix dot product for vector search embeddings}
- Performance Bottleneck: {L1 Data Cache Misses & Non-Contiguous Memory Stride}
- Target SIMD Instruction Set: {AVX-512 FMA (512-bit zmm registers)}

### MANDATORY FORMAL REASONING:
1. <think>
   - Analyze Static Single Assignment (SSA) form and identify memory alias hazards.
   - Calculate loop trip count and evaluate auto-vectorization feasibility (`vector.body` width = 4 or 8).
   - Model register pressure: ensure hot variables stay inside xmm/ymm/zmm vector registers without spilling to stack.
   - Verify branch prediction entropy and apply `llvm.expect` branch weight hints.
   - Check memory alignment invariants (32-byte or 64-byte aligned load/store instructions).
</think>

### OPTIMIZATION DELIVERABLES:
1. **Optimized LLVM IR (SSA)**: Clean, vectorized LLVM IR using `target-cpu` features.
2. **Target Assembly Verification**: Annotated x86-64 / ARM64 assembly disassembly highlighting unrolled inner loops.
3. **Benchmark Hypotheses**: Theoretical instruction count reduction and L1 cache line hit improvement.

Source Implementation:
{float cosine_similarity(const float* a, const float* b, size_t n) {
  float dot = 0.0f, norm_a = 0.0f, norm_b = 0.0f;
  for (size_t i = 0; i < n; ++i) {
    dot += a[i] * b[i];
    norm_a += a[i] * a[i];
    norm_b += b[i] * b[i];
  }
  return dot / (sqrtf(norm_a) * sqrtf(norm_b));
}}